In a scan test, an increase in power consumption leads to IR drop, a temporary drop in the power supply voltage. In some cases, this leads to a malfunction of a logic circuit, resulting in a scan flip-flop acquiring and holding an erroneous test response value. This leads to the occurrence of error in a test, in which a given logic circuit is judged to be defective even if it operates normally in a normal operation. As a result, such a test leads to yield loss. In particular, in a case in which a semiconductor logic circuit is configured with a very fine size on a very large scale and configured to operate with a low power supply voltage, such test error leads to a marked yield loss. Thus, it is important to reduce the power consumption in the scan test.
The power consumption in the scan test is roughly classified into two kinds, i.e., power consumption in a capture mode (capture power) and power consumption in a shift mode (shift power). Furthermore, the shift power is classified into two kinds, i.e., power consumption required for a scan-in operation and power consumption required for a scan-out operation. From among the aforementioned kinds of power consumption, the present inventors have developed a fault detection system which is capable of reducing the capture power (see Patent document 1) and a fault detection system which is capable of reducing the shift power required for a scan-in operation (see Patent document 2).